The single crystal of silicon carbide (SiC), as compared with the single crystal of silicon (Si), possesses excellent physical properties such as a wide band gap, large dielectric breakdown strength and a large saturated drift velocity of electrons. By using SiC as a starting material, therefore, it is made feasible to fabricate a semiconductor device for electric power exhibiting high blocking voltage and low resistance and surpassing the limits of Si. Further, SiC is characterized, similarly to Si, by being capable of forming an insulating layer by thermal oxidation. From these facts, it is inferred that a vertical MOSFET of high blocking voltage and low on-resistance is realized by using a single crystal of SiC as a material. Thus, many researches and developments directed toward this realization are now under way.
When SiC is used as raw material, a vertical MOSFET cannot be fabricated by the double diffusion method that is generally adopted for Si. This is because no channel region can be formed by the difference in diffusion length in the lateral direction between a p and an n type impurity because of an extremely small diffusion coefficient of an impurity element within the single crystal of SiC. A -vertical MOSFET analogous to the D-MOSFET of Si, therefore, is prepared by the ion implantation of a p and an n type impurity. By this method, however, the electron mobility is degraded because numerous crystal defects induced by the ion implantation are left behind in the channel region and suffered to scatter the conduction electrons induced within the channel. The SiC vertical MOSFET prepared by the double ion implantation method has an extremely small channel mobility of not more than 5 cm2/Vs as compared with that of the D-MOSFET of Si, which is about 500 cm2/Vs. As a result, it encounters the problem that the on-resistance thereof will be far higher than the theoretical value.
As a means to solve this problem, the structure that has a channel region formed not by ion implantation but with a deposit film has been proposed, A typical example of this structure is disclosed in Patent Document 1. FIG. 8 is a cross section of a unit cell thereof. In this structure, a low-density n-type SiC drift layer 2 is deposited on a high-density n-type SiC substrate 1, a high-density p-type SiC gate layer 3 possessing a first deficient part 21 is formed by ion implantation on the surface of the n-type drift layer 2, and a low-density p-type SiC layer 5 is further deposited thereon. On the surface part of the low-density p-type layer 5, an n-type source layer 4 is selectively formed by ion implantation, a gate electrode 10 is formed via a gate oxide film 7, a source electrode 9 is further formed via an interlayer insulating film 11, respectively, and a channel region 51 is formed in a low-density p-type deposit layer 5 lying directly below the gate oxide film 10. The structure is characterized by the fact that an n-type base layer 61 penetrating the low-density p-type deposit layer 5 and reaching the n-type drift layer 2 of the first deficient part 21 is caused by the ion implantation of an n-type impurity via the surface thereof to selectively form a region having the p-type deposit layer inverted to an n-type (hereinafter, this n-type base layer 61 will be referred to as “ion-implantation polarity-inversion layer”). In this structure, since the channel region 51 is formed in the low-density p-type deposit layer having undergone no ion implantation, it is enabled to obtain high mobility of conduction electrons and fabricate a vertical MOSFET of small on-resistance. The structure is characterized by the fact that in the state of stopping potential, the leak of electric field as to the gate oxide film near the channel region 51 can be prevented and the source and drain blocking voltage can be heightened because the vertical channel part 21 is completely pinched off at low voltage with the depletion layer diverging in the lateral direction from the high-density p-type gate layer 3 toward the low-density n-type drift layer 2.
In the MOSFET of this conventional structure, the region that is composed of the source electrode 9, a part 52 of the low-density p-type deposit layer 5 connected with low resistance to the source electrode, the p-type gate layer 3 projected in the direction of the thickness thereof, the n-type drift layer 2, the high-density n-type substrate 1 and a drain electrode 8 is made to form a diode region to be built in the MOSFET.
When the MOSFET of this description is used in the inverter device with such a dielectric load as an electric motor, the return current generated by the energy accumulated in the load is conducted to the built-in diode region. At times dependent on the mode of operation, the possibility that the magnitude of the electric current conducted to the diode will equal that of MOSFET and that the operating commitment of current conduction will exceed 50% of its total may arise. The MOSFET that is used in an inverter device having high conversion efficiency, therefore, is required to incur the least possible loss of current conduction in the built-in diode region.
The conventional MOSFET disclosed in FIG. 8 and using SiC as raw material, however, has the problem of increasing the forward voltage drop in a built-in diode region. That is, the p-n junction diode of SiC having a wide band gap, for the purpose of conducting electric current in the forward direction, necessitates a forward bias exceeding a blocking-state voltage of not less than 2.5 V to 3.0 V and consequently notably increases the forward voltage drop as compared with a MOFET using Si as raw material.    Patent Document 1: International Publication 2004-036655